1. Field of the Invention
The present invention relates to a liquid crystal display device (LCD), and more particularly, to a thin film transistor (TFT) array substrate and a method of manufacturing the same that is capable of decreasing the number of usage of exposure masks to reduce the process time and the process costs and excessively etching a passivation film below a photoresist pattern to easily perform a lift-off process of the photoresist pattern.
2. Discussion of the Related Art
A liquid crystal display device has a high contrast ratio, is suitable for gradation display or motion picture display, and has low power consumption. For this reason, relative importance of the liquid crystal display device is being increased among flat panel display devices.
In such a liquid crystal display device, various patterns, such as drive devices or lines, are formed on a substrate for performing an operation. One of general technologies used to form patterns is photolithography.
The photolithography includes a series of complicated processes for applying photoresist, a material which is exposed to ultraviolet rays, to a film layer on a substrate to which patterns will be formed, developing the photoresist by exposing a pattern formed at an exposure mask on the photoresist, etching the film layer using the patterned photoresist as a mask, and stripping the photoresist.
In a conventional thin film transistor (TFT) array substrate for liquid crystal display devices, five to seven mask technologies are normally used to form a gate line layer, a gate insulation film, a semiconductor layer, a data line layer, a passivation film, and a pixel electrode on a substrate. As the number of usage of photolithography using masks is increased, a probability of process error is increased.
In order to solve the above-mentioned problem, research has been conducted on a low-mask technology for minimizing the number of photolithography processes to increase the productivity and secure the process margin.
Hereinafter, a method of manufacturing a conventional TFT array substrate will be described with reference to the accompanying drawings.
FIGS. 1A to 1E are sectional views illustrating a process for manufacturing the conventional TFT array substrate.
So as to form the conventional TFT array substrate, which is used for liquid crystal display devices, as shown in FIG. 1A, a low-resistance metal material, such as copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), or chrome (Cr), is deposited on a substrate 11. Subsequently, a plurality of gate lines (not shown), a gate electrode 12a, and a gate pad 22 are formed on the deposited metal material through a photolithography process and an etching process using a first mask.
The photolithography process and the etching process are performed as follows.
A low-resistance metal material is deposited on a transparent glass substrate 11 having high heat resistance at high temperature. Photoresist is applied to the deposited metal material. A first mask having a pattern layer is placed on the photoresist, and light is selectively irradiated to the photoresist. As a result, the same pattern as the first mask is formed on the photoresist.
Subsequently, the photoresist to which the light was irradiated is removed using a developing solution so as to pattern the photoresist. The metal material exposed through the patterned photoresist is selectively etched so as to obtain a desired pattern.
Subsequently, as shown in FIG. 1B, an inorganic material, such as silicon nitride (SiNx) or silicon oxide (SiOx), is deposited on the front surface of the substrate 11 including the gate electrode 12a at high temperature so as to form a gate insulation film 13.
Subsequently, amorphous silicon is deposited on the gate insulation film 13, and the amorphous silicon is patterned through a photolithography process using a second mask so as to form an island-shaped semiconductor layer 14 on the gate insulation film 13 such that the semiconductor layer 14 overlaps with the gate electrode 12a. 
Subsequently, as shown in FIG. 1C, a low-resistance metal material, such as copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), or chrome (Cr), is deposited on the front surface of the substrate 11 including the semiconductor layer 14, and then a data line layer is formed on the deposited metal material through a photolithography process using a third mask.
The data line layer includes data lines (not shown) intersecting the gate lines for defining a unit pixel region, a source electrode 15a overlapping with the edge of the semiconductor layer 14, a drain electrode 15b, and a data pad 25 located at a pad region.
The gate electrode 12a, the gate insulation film 13, the semiconductor layer 14, the source electrode 15a, and the drain electrode 15b, which are deposited as described above, constitute a thin film transistor that controls on/off of voltage applied to the unit pixel.
Subsequently, as shown in FIG. 1D, an organic insulating material, such as benzocyclobutene (BCB), or an inorganic insulating material, such as silicon nitride (SiNx), is deposited on the front surface of the substrate 11 including the drain electrode 15b so as to form a passivation film 16. The passivation film 16 is partially removed through a photolithography process using a fourth mask so as to form a contact hole 71 through which the drain electrode 15b is exposed, a first pad opening region 81a through which the gate pad 22 is exposed, and a second pad opening region 81b through which the data pad 25 is exposed.
Subsequently, as shown in FIG. 1E, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the front surface of the substrate 11 including the passivation film 16, and a pixel electrode 17 is formed at a pixel region, such that the pixel electrode 17 is electrically connected to the drain electrode 15b, through a photolithography process using a fifth mask, thereby completing a TFT array substrate. At the same time, a transparent conductive layer 27 is formed for covering the first and second pad opening regions 81a and 81b to prevent the oxidation of the gate pad 22 and the data pad 25.
In the conventional TFT array substrate for liquid crystal display devices, the exposure masks are used at least five times so as to form the gate line layer, the semiconductor layer, the data line layer, the contact hole of the passivation film, and the pixel electrode. When the number of usage of the exposure masks is increased, the process for manufacturing the TFT array substrate is complicated with the result that the process time and the process costs are increased. Consequently, the process efficiency is greatly lowered.